Today's consumer electronics market frequently demands complex functions requiring very intricate circuitry. Scaling to smaller and smaller fundamental building blocks, e.g. transistors, has enabled the incorporation of even more intricate circuitry on a single die with each progressive generation. Semiconductor packages are used for protecting an integrated circuit (IC) chip or die, and also to provide the die with an electrical interface to external circuitry. With the increasing demand for smaller electronic devices, semiconductor packages are designed to be even more compact and must support larger circuit density. For example, some semiconductor packages now use a coreless substrate, which does not include the thick resin core layer commonly found in conventional substrates. Furthermore, the demand for higher performance devices results in a need for an improved semiconductor package that enables a thin packaging profile and low overall warpage compatible with subsequent assembly processing.
On the other hand, although scaling is typically viewed as a reduction in size, the size of a particular semiconductor die may in fact be increased in order to include multi-functional components on a single die. However, structural issue may arise when attempting to package larger scale semiconductor die in a semiconductor package. For example, the effect of differences in the coefficients of thermal expansion (CTE) between components used in a semiconductor package can lead to detrimental defects as a result of performing the semiconductor die packaging process.